GATE CSE: Computer organisation

Question 1 of 10

A 5-stage pipeline with no stalls runs 100 instructions. How many clock cycles does it take?

Question 2 of 10

For a very long instruction stream, the ideal speedup of a k-stage pipeline approaches:

Question 3 of 10

A 32 KB direct-mapped cache has 64-byte blocks. How many cache lines does it have?

Question 4 of 10

That cache (32 KB, direct-mapped, 64 B blocks) with 32-bit addresses uses how many tag bits?

Question 5 of 10

Hit time 1 ns, miss rate 5%, miss penalty 100 ns. The average memory access time is:

Question 6 of 10

An instruction that needs the result of the instruction just before it causes a:

Question 7 of 10

Operand forwarding (bypassing) reduces stalls caused by:

Question 8 of 10

A 2-way set-associative cache with 128 lines has how many sets?

Question 9 of 10

DMA lets:

Question 10 of 10

A little-endian machine stores the 32-bit value 0x12345678 with which byte at the lowest address?